1. Field of the Invention
The invention relates to integrated circuits for economically processing digital information produced in response to optical scanning of bar coded labels.
2. Description of the Prior Art
The size of an integrated circuit, i.e., the "chip size", is an important factor in the ultimate cost of the integrated circuit to the final user. Another important cost is the engineering and design cost. The larger the number of units of the integrated circuit which are manufactured, the smaller are the engineering and design costs per unit. However, the chip size becomes an increasingly dominant factor in the ultimate product cost as the manufacturing volume of the product increases. For state of the art MOS (metal-oxide-semiconductor) large scale integrated (LSI) devices, very large numbers of MOSFETS (metal-oxide-semiconductor field effect transistors) are fabricated on a single monolithic silicon "chip" which is frequently less than 250 mils square. Thousands of conductive lines, some composed of polycrystalline silicon and others composed of aluminum, interconnect the various elements of the MOSFETS. Minimum line widths and spacings between the respective lines and the MOSFETS must be maintained to avoid short circuits and parasitic effects. Yet the length of the interconnecting lines and their associated capacitances must be minimized not only to reduce chip size, but also to achieve maximum circuit operating speeds. A wide variety of trade-offs, including the necessity to minimize chip size, increase circuit operating speed, reduce power consumption, and achieve acceptable reliability are involved in obtaining an optimum "layout" or arrangement of MOSFETS and interconnection pattern therebetween in order to obtain a MOSLSI circuit which is both economical and has acceptable operating characteristics. Often, the technical and commercial success of an electronic product utilizing MOSLSI technology may hinge on the ability of the chip designer to achieve an optimum chip topography.
A very high level of creative interaction between the circuit designer and the chip designer or layout draftsman is required to achieve a chip topography or layout which enables the integrated circuit to have acceptable operating speed and power dissipation and yet is sufficiently small to be economically feasible. Months of such interaction resulting in numerous trial layout designs and redesigns and circuit design revisions may be required to arrive at an optimum topography for a single MOSLSI chip. Although the computer aided design (CAD) approach in the past has been attempted in order to generate optimum MOSLSI topography designs, this approach has been only moderately successful, and only to the extent that the CAD approach sometimes provides a rapid chip topography design. However, such a topography design usually has mediocre performance and usually results in unduly large, uneconomical semiconductor chips. It is well established in the integrated circuit industry that CAD approaches to generating MOSLSI chip layouts do not yet come close to achieving the topography design optimization which can be accomplished by human ingenuity applied to the task.
Some of the numerous design constraints faced by the MOSLSI chip designer include specifications for the minimum widths and spacing of diffused regions in the silicon, the minimum size required for contact openings in the insulating field oxide, the spacings required between the edges of contact openings to the edge of diffused regions, minimum widths and spacing of polycrystalline silicon conductors, the fact that such polycrystalline silicon conductors cannot "cross over" diffused regions, the minimum widths and spacings between the aluminum conductors, and the constraint that conductors on the same layer of insulating oxide cannot cross over like conductors. The high amount of capacitance associated with diffused regions and the resistances of both diffused regions and the polycrystalline silicon conductors must be carefully considered by the circuit designer and the chip designer in arriving at an optimum chip topography.
For many types of logic circuits, such as those in the present invention, a very large number of conductive lines between sections of the logic circuitry are required. The practically infinite number of possibilities for routing the various conductors and placing the various MOSFETS taxes the skill and ingenuity of even the most skillful chip designers and circuit designers, and is beyond the capability of the most sophisticated computer programs yet available.
Other constraints faced by the chip designer and circuit designer involve the need to minimize cross coupling and parasitic effects which occur between various conductive lines and conductive regions. Such effects may degrade voltages on various conductors, leading to inoperative circuitry or low reliability operations under certain operating conditions.
Accordingly, it is an object of the present invention to provide an integrated circuit pattern recognition array for processing digital signals produced in response to optical scanning of a bar coded label, which integrated circuit has a topography which provides maximum possible circuit operating speed with lowest possible chip size and power dissipation.